Recently, a solid state drive (SSD) configured to have plural NAND-type flash memories and a controller has been used for a server apparatus, a laptop PC, a net-book and the like. As the NAND-type flash memory, a memory having an upper limit in an erase count, in which a data write size and a data erase size are markedly different is widely known. Patent Literatures 1, 2, 3, and 4 disclose a control method of such an NAND-type flash memory. For example, Patent Literature 1 discloses a technique in which a write pointer that sequentially sets a write address while circulating through addresses of the flash memory in a predefined order is provided and wear leveling is performed using a correspondence relationship between the write pointer and a logical address or a circulation count of the write pointer. Further, Patent Literature 5 discloses a NAND-type flash memory of a three-dimensional structure.
In addition, as a technique reviewed by the inventors, there is a semiconductor device including a phase change memory, for example. Such a memory uses a chalcogenide material (or phase change material) such as a Ge—Sb—Te system including at least antimony (Sb) and tellurium (Te) or an Ag—In—Sb—Te system as a material of a recording layer. Further, a diode is used as a selection element thereof. Characteristics of such a phase change memory that uses the chalcogenide material and the diode are disclosed in Non-Patent Literature 1, for example.
FIG. 29 is a diagram illustrating a relationship between a pulse width and a temperature necessary for phase change of a resistance storage element using a phase change material. A vertical axis represents temperature, and a horizontal axis represents time. When storage information “0” is written to a storage element, as shown in FIG. 29, a reset pulse for heating the element at a melting point Ta of the chalcogenide material or higher and then cooling the element is applied. By shortening cooling time t1 (for example, by setting cooling time t1 to about 1 ns), the chalcogenide material is in a high resistance amorphous state.
In contrast, when storage information “1” is written, a set pulse for maintaining the storage element in a temperature area that is lower than the melting point Ta but is higher than a crystallization temperature Tx (which is equal to or higher than a glass transition point) is applied. Thus, the chalcogenide material is in a low resistance polycrystalline state. Time t2 necessary for crystallization varies according to the composition of the chalcogenide material. The temperature of the element shown in FIG. 29 depends on Joule heat emitted by the storage element itself and thermal diffusion to the surroundings.
Further, as disclosed in Non-Patent Literature 2, if the phase change memory has a small resistance element structure, power necessary for state change of a phase change film is reduced. Thus, the phase change memory is in principle suitable to miniaturization, prompting research to be actively conducted. Further, Non-Patent Literature 3 discloses a phase change memory in which a time of about 120 ns is necessary for decrease of resistance of the chalcogenide material and a time of about 50 ns is necessary for increase of the resistance.
Furthermore, Patent Literatures 6 and 7 disclose a nonvolatile memory of a three-dimensional structure. Patent Literature 6 discloses a configuration in which memory cells that are provided with a variable resistance element and a transistor connected in parallel to the variable resistance element are connected in series in a stacked direction. Patent Literature 7 discloses a configuration in which memory cells that are provided with a variable resistance element and a diode connected in series to the variable resistance element are connected in series in a stacked direction with a conductive line being interposed therebetween. In this configuration, for example, by assigning a potential difference between a conductive line between two memory cells and two conductive lines outside the two memory cells, a writing operation is collectively performed with respect to two memory cells.